(1) Field of the Invention
The present invention relates generally to a structure of and manufacturing process for a semiconductor device which provides improved ESD protection of active semiconductor devices and more particularly to a Vcc to Vss protection element for complimentary metal oxide semiconductor (CMOS) circuit configuration.
(2) Description of Prior Art
Because of high input impedance and thin oxide gate structures, the problem of Electrostatic Discharge (ESD) damage with field effect transistor (FET) devices can be severe. Therefore the input/output I/O circuit locations or pads usually have a protective device connected between the I/O pad and the internal circuits which allows the ESD current to be shunted to ground. Another important characteristic of the ESD protection device is that it must not interfere with the operation of the devices it is designed to protect, while at the same time providing good protection when abnormal or ESD voltage incidents occur.
A representative logic circuit with prior art ESD protection for the I/O logic circuitry is shown in FIG. 1A. Section 4 in FIG. 1A shows the logic output pre-driver section, with outputs IN1 and IN2 feeding the driver and internal logic ESD protection string 6. IN1 feeds the gate of used P channel metal oxide semiconductor (PMOS) PU1 which is on for low IN1 signals presenting a high voltage of approximately Vcc at the I/O pad 8. Output IN2 feeds the gate of a N channel metal oxide semiconductor (NMOS) NU2 which, when IN2 is high, is on presenting a low voltage to I/O pad 8.
The typical logic I/O ESD protection device consists of a NMOS NU1 with the drain connected to the I/O pad 8. A parasitic NPN bipolar device, not shown in FIG. 1A, is essentially in parallel with the NMOS device and has a collector base junction breakdown triggered by the ESD voltage. A Pxe2x88x92 dopant region 28 beneath the N+ drain region of NU1 has the effect of reducing the collector base junction breakdown voltage. Once triggered by an ESD incident, the parasitic device operates in a secondary breakdown mode to clamp the ESD voltage to a suitable level and pass the high current to a second voltage source Vss, typically ground. Section 7 in FIG. 1A represents a conventional Vcc to Vss ESD NMOS protection device without any special diffusions in its elements.
A typical N channel logic and I/O FET protection device cross section is depicted in FIG. 1B. An N-channel FET is situated on a P-substrate 10. The device consists of field oxide isolation (FOX) regions 12, a gate structure consisting of a conducting element 16 typically polysilicon, with a gate insulation oxide 14, and oxide spacers 18. The gate and FOX are shown covered with an insulation layer 20, typically silicon oxide (SiO2) or borophosphosilicate glass (BPSG). Not depicted for clarity are the electrical contact and conductor details. The source 22 and drain 24 elements consist of lightly doped N regions (LDD) 26 and heavily doped N+ regions for source 22 and drain 24. Incorporated beneath the N+ drain region 24 is a Pxe2x88x92 region 28 which is typically created by implanting boron through the pre-metal contact openings.
The P dopant concentration in the Pxe2x88x92 area 28 is higher than that in the substrate in general. Junction breakdown is inversely proportional to the impurity concentration. Therefore, the Pxe2x88x92 region lowers the drain to substrate junction breakdown voltage by increasing the substrate impurity concentration at the junction boundary. This effect enhances the ESD protection of the device. Note that the Pxe2x88x92 region 28 in prior art is contained near the center of the drain region 24 in a region smaller than the drain region 24 and does not approach the drain areas near the edge of the gate.
In addition to the specific diffusion design of the conventional ESD protection device, the conventional prior art device is placed to protect ESD events with respect to the I/O pad.
Often overlooked is the need for improved ESD protection between the power buses, typically called Vcc and Vss. ESD voltages and energy can be coupled to the Vss bus, and can cause high channel current for devices in the xe2x80x9conxe2x80x9d state as well as cause high gate stresses for devices in electrical proximity to the Vss bus. The result is degradation in overall IC chip and circuit ESD protection performance.
The invention describes a method and ESD IC power bus protection device with enhanced ESD protection capability.
The following patents describe ESD protection devices.
U.S. Pat. No. 5,898,205 (Lee) describes an ESD protection circuit using NMOS and PMOS devices.
U.S. Pat. No. 5,953,601 (Shiue et al.) discloses an ESD implantation step using boron. The ion implantation is spaced from the polysilicon gate.
U.S. Pat. No. 5,929,493 (Wu) teaches a CMOS process using blanket, low dose boron implant to adjust Vth for ESD protection devices.
U.S. Pat. No. 5,559,352 (Hsue et al.) discloses a method to improve an ESD protection device using ion implantation. The implantation is spaced from the polysilicon gate.
Accordingly, it is the primary objective of the invention to provide a novel, effective device structure, and a device development method, for protecting integrated circuits from damage caused by ESD events occurring during circuit operation, in particular for ESD events between Vcc and Vss power lines.
In addition, it is an objective of this invention to provide this ESD protection while maintaining appropriate normal circuit operating parameters of the devices being protected.
It is yet another object of the invention to provide a process method for forming the ESD protection structure that is fully compatible with the manufacturing process of the devices being protected.
The above objectives are achieved in accordance with the embodiments of the invention that describes a process and novel structure for a ESD protection NMOS FET device for the integrated circuit (IC) power bus elements, typically known as Vcc and Vss. A NMOS FET device is created between the Vcc and Vss power buses with the source connected directly to Vss, or ground. The device gate is connected to Vss through a resistor and the device drain is connected to Vcc.
A particularly unique feature of the invention is an acceptor specie implant, typically boron, into the device drain region. This implant produces a Pxe2x88x92 region around and below the N+ device drain and extends into proximity of, or has a small overlap with the gate channel area. As previously noted, the junction breakdown voltage is inversely proportional to the doping levels at the junction boundary region. The special acceptor implant produces a Nxe2x88x92 region of higher concentration than the substrate, and hence reduces the breakdown voltage of the P-N junction. This allows for a higher ESD discharge current for a given power, since power is a product of current times voltage. Since the device is placed between the voltage buses, junction capacitance is not as critical a factor as it is for the active logic circuits.
A NPN parasitic bipolar transistor exists in parallel with the NMOS device, with the collector formed with the NMOS drain, the P base formed by the P substrate, and the collector formed with the NMOS drain. A high voltage from an ESD event on the Vcc power bus causes the PN collector junction to breakdown, raising the substrate voltage providing positive base voltage further enhancing turn on of the parasitic NPN transistor causing the ESD current to be shunted to Vss preventing damage to the active devices. In addition, if the ESD energy is sufficient, hot carrier tunneling will occur causing a positive voltage to appear on the NFET gate also turning on that device shunting additional ESD current to Vss.
The gate of the NMOS ESD device is connected to Vss or ground through a resistor, assuring that the device is in the off state during normal circuit operation and therefore it does not impact normal circuit operation.